1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically to a semiconductor device containing a gate electrode and a contact connected to the gate electrode.
2. Related Art
Japanese Laid-Open Patent Publication No. H5-48022 describes a configuration in which a common gate electrode is disposed as extending over a P-type diffusion region composing a P-channel MOS transistor and an N-type diffusion region composing an N-channel MOS transistor, wherein the gate electrode is widened in the portion thereof which falls between the P-type diffusion region and the N-type diffusion region, as compared with the portion thereof which falls on these diffusion regions, and a contact connecting the gate electrode and an interconnect formed on the upper layer is provided on the widened portion of the gate electrode.
Japanese Laid-Open Patent Publication No. H11-195704 describes a semiconductor device configured as having a stopper film on a gate electrode, and an insulating interlayer formed further thereon so as to cover the gate electrode. The stopper film is composed of a material showing a larger etching selectivity than the insulating interlayer shows.
FIG. 6 is a plan view showing a configuration of a conventional semiconductor device similar to that described in Japanese Laid-Open Patent Publication No. H5-48022. FIG. 7 and FIG. 8 are an E-F sectional view and a G-H sectional view, respectively, of FIG. 6.
A semiconductor device 10 contains a semiconductor substrate 1, and impurity-diffused regions 2 and device isolation insulating films 4 formed in the surficial portion of the semiconductor substrate 1. The semiconductor device 10 further contains a plurality of gate electrodes 8 extending over the impurity-diffused regions 2 and the device isolation insulating films 4 of the semiconductor substrate 1. Each of the gate electrodes 8 of the semiconductor device 10 contains a pedestal 9 formed wider in width on the device isolation insulating film 4, than on the impurity-diffused regions 2. The semiconductor device 10 still further contains contacts 11 formed on the gate electrodes 8 as being connected to the gate electrodes 8 at the wider portion thereof.
Thus-configured semiconductor device 10 can be formed typically by the procedures below. First, a silicon nitride film or the like is formed over the entire surface of the semiconductor substrate 1 typically by the CVD process. Next, regions of the silicon nitride film, destined for formation of the device isolation insulating films 4, are selectively removed with the aid of a lithographic technique. Next, trenches in which the device isolation insulating films 4 will be formed later are formed in the semiconductor substrate 1 by an etching technique through the silicon nitride film used as a mask. Thereafter, a silicon oxide film is formed over the entire surface of the semiconductor substrate 1 by the CVD process, so as to fill the trenches with the silicon oxide film. Next, portions of the silicon oxide film exposed out into the external are removed by a CMP technique, so as to planarize the surface. Before the trenches are filled up with the silicon oxide film, it is also allowable herein to form a liner film composed of a silicon nitride film or the like on the side walls of the trenches, typically by the thermal oxidation process or the CVD process. The silicon nitride film, used as the mask in the process of forming the trenches, are then removed typically by wet etching.
Next, with the aid of a lithographic technique and an ion implantation technique, ion is introduced into the channel portions and so forth, to thereby form the impurity-diffused regions 2. Next, an electrode material layer for composing the gate electrodes 8 is formed over the entire surface of the semiconductor substrate 1, and the film is then patterned to thereby form the gate electrodes 8. Also the pedestals 9 are formed at the same time. The pedestals 9 are composed of a material same as that composing the gate electrodes 8.
Thereafter, the impurity-diffused regions 2 are further subjected to some processes including ion implantation through the gate electrodes 8 used as a mask. The impurity-diffused regions 2 are then activated by annealing. Transistors are formed as a consequence. An insulating interlayer 12 is then formed over the entire surface of the semiconductor substrate 1. With the aid of a lithographic technique and an etching technique, contact holes are then formed in the insulating interlayer 12. Next, the contact holes are filled up with an electro-conductive material such as tungsten, to thereby form the contacts 11.
Because the gate electrodes 8 have, formed therein, the pedestals 9 widened in width in the connecting portions of the gate electrodes 8 and the contacts 11 as shown in FIG. 6, the surface of the semiconductor substrate 1 can be protected by the pedestals 9 of the gate electrodes 8, when the contact holes are formed in the insulating interlayer 12. The surface of the semiconductor substrate 1 can therefore be prevented from being etched, even for the case where the width of the contacts 11 is larger than that of the gate electrodes 8, or for the case where the pattern should be misaligned.